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datasheet 28-bit 1:2 registered buffer with parity idt74sstubf32865a 28-bit 1:2 registered buffer with parity 1 idt74sstubf32865a 7092/10 description this 28-bit 1:2 registered buffer with parity is designed for 1.7v to 1.9v v dd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8 v cmos drivers that have been optimized to drive the ddr2 dimm load. the idt74sstubf32865a operates from a differential clock (clk and clk ). data are registered at the crossing of clk going high, and clk going low. the device supports low-power standby operation. when the reset input (reset ) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (v ref ) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs except ptyerr are forced low. the lvcmos reset input must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. in the ddr2 rdimm application, reset is specified to be completely asynchronous with respect to clk and clk . therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the out puts will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, th e register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the idt74sstubf32865a must ensure that the outputs will remain low, thus ensuring no glitches on the output. the device monitors both dcs0 and dcs1 inputs and will gate the qn outputs from changing states when both dcs0 and dcs1 are high. if either dcs0 and dcs1 input is low, the qn outputs will function normally. the reset input has priority over the dcs0 and dcs1 control and will force the qn outputs low and the ptyerr output high. if the dcs-control functionality is not desired, then the csgateenable input can be hardwired to ground, in which case, the setup-time requirement for dcs would be the same as for the other d data inputs. the idt74sstubf32865a includes a parity checking function. the idt74sstubf32865a accepts a parity bit from the memory controller at its input pin parin, compares it with the data received on the d-inputs and indicates whether a parity error has occurred on its open-drain ptyerr pin (active low). features ? 28-bit 1:2 registered buffer with parity check functionality ? supports sstl_18 jedec specification on data inputs and outputs ? supports lvcmos switching levels on csgateen and reset inputs ? low voltage operation: v dd = 1.7v to 1.9v ? available in 160-ball lfbga package applications ? ddr2 memory modules ? provides complete d dr dimm solution with ics98ulpa877a or idtcspua877a ? ideal for ddr2 400, 5 33, 667, and 800
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 2 idt74sstubf32865a 7092/10 block diagram qodt0a, qodt1a qodt0b, qodt1b qcs1a qcs1b qcs0a qcs0b q21b q21a qcke0a, qcke1a qcke0b, qcke1b q0b q0a d r q d r q d r q d r q d r q d r q ptyerr parity generator and checker d r q 22 2 2 2 2 v ref parin d0 d21 dcs0 csgateen dcs1 dcke0, dcke1 dodt0, dodt1 reset clk clk (cs active)
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 3 idt74sstubf32865a 7092/10 pin configuration 160-ball bga top view note: 1. an empty cell indicates no ball is populated at that gridpoint. nc denotes a no-connect (ball present but not connected to the die). mcl denotes a pin that must be connected low. mch denotes a pin that must be connected high. 160-ball bga top view a b c d e f g h j k l m n p r t u v 1234 5 678 910 11 12 6 qcke1b v ddl nc qcke1a v ddl v ddl gnd d20 dodt0 d13 dodt1 r t q15b q14b 11 qodt0b qodt1b q16b q1b qcs1b q6b q5b q20b q17b qcs0b q2b q10b q9b q11b q0b q0a gnd gnd gnd v ddl 5 nc gnd gnd v ddl gnd gnd gnd nc gnd gnd gnd v ddl v ddl 4 nc v ddl v ddl v ddl gnd v ddl v ddl nc gnd v ddl gnd v ddl gnd 3 nc parin 2 d2 d4 d8 d9 dcs1 d14 d15 d5 dcs0 d12 nc d10 d16 d21 1 d1 d3 d7 d11 clk reset clk csgate en d6 v ref d18 d0 d17 d19 b c e f k l h d a j g m n p 12 qodt0a qodt1a q16a q1a qcs1a q6a q5a q20a q17a qcs0a q2a q10a q15a q14a q9a q11a q8b q8a 10 q18a 9 gnd v ddr gnd v ddr gnd gnd q19a v ddr v ddr gnd v ddr gnd 8 gnd v ddr gnd v ddr gnd gnd v ddr v ddr q21a gnd v ddr v ddr 7 v ddr nc qcke0a v ddr q3b q3a mch mch ptyerr nc mcl mcl dcke1 mcl dcke0 v ref u v q13b q4b q7b q12b q13a q4a q7a q12a q18b q19b q21b qcke0b
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 4 idt74sstubf32865a 7092/10 ball assignment signal group signal name type description ungated inputs dcke0, dcke1, dodt0, dodt1 sstl_18 dram function pins not associated with chip select. chip select gated inputs d0 ... d21 sstl_18 dram inputs, re-driven only when chip select is low. chip select inputs dcs0 , dcs1 sstl_18 dram chip select signals. these pins initiate dram address/command decodes, and as such at least one will be low when a valid add ress/command is present. the register can be programmed to re-drive all d-inputs only (csgateen high) when at least one chip select input is low. re-driven q0a...q21a, q0b...q21b, qcsna,b qckena,b, qodtna,b sstl_18 outputs of the register, valid after the specified clock count outputs and immediately following a rising edge of the clock. parity input parin sstl_18 input parity is received on pin parin and should maintain odd parity across the d0...d21 inputs, at the rising edge of the clock. parity error ptyerr open drain when low, this output indicates that a parity error was output identified associated with the address and/or command inputs. ptyerr will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with fi nal parity out timing on the industry-standard ddr-ii register with parity (in jedec definition). program inputs csgateen 1.8v lvcmos chip select gate enable. when high, the d0..d21 inputs will be latched only when at least one chip select input is low during the rising edge of the clock. when low, the d0... d21 inputs will be latched and redriven on every rising edge of the clock. clock inputs clk, clk sstl_18 differential master clock input pair to the register. the register operation is triggered by a rising edge on the positive clock input (clk). miscellaneous inputs mcl, mch must be connected to a logic low or high. reset sstl_18 asynchronous reset input. when low, it causes a reset of the internal latches, thereby forcing the outputs low. reset also resets the ptyerr signal. v ref 0.9v nominal input reference voltage for the sstl_18 inputs. two pins (internally tied together) are used for increased reliability.
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 5 idt74sstubf32865a 7092/10 function table inputs 1 outputs reset dcs0 dcs1 csgate en clk clk dn, dodtn, dcken qn qcs0x qcs1x qodt, qcke hll x lllll hll x hhllh h l l x l or h l or h x q 0 q 0 q 0 q 0 hlhx lllhl hlhx hhlhh h l h x l or h l or h x q 0 q 0 q 0 q 0 hhl x llhll hhl x hhhlh h h l x l or h l or h x q 0 q 0 q 0 q 0 hhh l llhhl hhh l hhhhh h h h l l or h l or h x q 0 q 0 q 0 q 0 hhh h lq 0 hh l hhh h hq 0 hhh h h h h l or h l or h x q 0 q 0 q 0 q 0 lx or floating x or floating x or floating x or floating x or floating x or floating llll 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 6 idt74sstubf32865a 7092/10 parity and standby function table inputs 1 outputs reset dcs0 dcs1 clk clk of inputs = h (d1 - d21) parin 2 ptyerr 3 hlx even l h hlx odd l l hlx even h l hlx odd h h hxl even l h hxl odd l l hxl even h l hxl odd h h hhh x x ptyerr 0 h x x l or h l or h x x ptyerr 0 lx or floating x or floating x or floating x or floating x or floating x or floating h 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2 parin arrives one clock cycle after the data to which it applies. 3 this transition assumes ptyerr is high at the crossing of clk going high and clk going low. if ptyerr is low, it stays latched low for two clock cycles or until reset is driven low.
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 7 idt74sstubf32865a 7092/10 absolute maximum ratings stresses greater than those listed under absolute maximum ratings ma y cause permanen t damage to the device. this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect reliability. item rating supply voltage, v dd -0.5v to 2.5v input voltage range, v i 1 1 the input and output negative voltage ratings may be exceeded if the ratings of the i/p and o/p clamp current are observed. -0.5v to v dd + 2.5v output voltage range, v o 1,2 2 this current will flow only when the output is in the high state level v o > v ddq . -0.5v to v ddq + 0.5v input clamp current, i ik 50ma output clamp current, i ok 50ma continuous output clamp current, i o 50ma continuous current through each v dd or gnd 100ma package thermal impedance ( ja) 3 3 the package thermal impedance is calculated in accordance with jesd 51. 0m/s airflow 44.3 c/w 1m/s airflow 38.1 c/w storage temperature -65 to +150 c
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 8 idt74sstubf32865a 7092/10 operating characteristics the reset and csgateen inputs of the device must be held at valid levels (not floating) to ensure proper device operation. the di fferential inputs must no t be floating unless reset is low. symbol parameter min. typ. max. units v dd i/o supply voltage 1.7 1.8 1.9 v v ref reference voltage 0.49 * v dd 0.5 * v dd 0.51 * v dd v v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v v i input voltage 0 v dd v v ih ac high-level input voltage dn, parin, dcsn , dcken, dodtn v ref + 0.25 v v il ac low-level input voltage v ref - 0.25 v ih dc high-level input voltage v ref + 0.125 v il dc low-level input voltage v ref - 0.125 v ih high-level input voltage reset , csgateen 0.65 * v ddq v v il low-level input voltage 0.35 * v ddq v icr common mode input range clk, clk 0.675 1.125 v v id differential input voltage 600 mv i oh high-level output current -8 ma i ol low-level output current 8 i errol ptyerr low level output current 25 ma t a operating free-air temperature 0 +70 c
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 9 idt74sstubf32865a 7092/10 dc electrical characterist ics over operating range following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, v dd = 1.8v 0.1v. symbol parameter test conditions min. typ. max. units v oh output high voltage i oh = -6ma, v ddq = 1.7v 1.2 v v ol output low voltage i ol = 6ma, v ddq = 1.7v 0.5 v v errol ptyerr output low voltage i errol = 25ma, v dd = 1.7v 0.5 v i il all inputs v i = v dd or gnd; v dd = 1.9v -5 +5 a i dd static standby i o = 0, v dd = 1.9v, reset = gnd 200 a static operating i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = clk = v ih ( ac ) or v il ( ac ) 10 ma i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = v ih ( ac ), clk = v il ( ac ) 120 i ddd dynamic operating (clock only) i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle 300 a/clock mhz dynamic operating (per each data input) i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. 40 a/clock mhz/ data c in dn, parin v i = v ref 350mv 2 3 pf clk and clk v icr = 1.25v, v ipp = 360mv 2.5 3.5 reset v i = v dd or gnd 5
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 10 idt74sstubf32865a 7092/10 timing requirements over recommend ed operating free-air temperature range switching characteristics over recommended free air operating range (unless otherwise noted) symbol parameter v dd = 1.8v 0.1v units min. max. f clock clock frequency 410 mhz t w pulse duration; clk, clk high or low 1 ns t act differential inputs active time 1 1 v ref must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of t act (max) after reset is taken high. 10 ns t inact differential inputs inactive time 2 2 v ref , data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of t inact (max) after reset is taken low. 15 ns t su setup time dcs0 before clk , clk , dcs and csgateen high; dcs1 before clk , clk , dcs0 and csgateen high 3 3 t su = 700ps for dcsx exiting suspention mode. 0.6 ns dcsn , dodt, dcke, and dn after clk , clk 0.5 parin after clk , clk 0.5 t h hold time dcsn , dodt, dcke, and dn after clk , clk 0.4 ns parin after clk , clk 0.4 symbol parameter v dd = 1.8v 0.1v units min. max. f max max input clock frequency 410 mhz t pdm 1 1 design target as per jedec specifications. propagation delay, single bit switching, clk to clk to qn 1.1 1.5 ns t pdq 2 2 production test. (see production test circu it in test circuit and waveform section.) propagation delay, single -bit switching, clk / clk to qn 0.4 0.8 ns t pdmss 1 propagation delay, simultaneous switching, clk to clk to qn 1.6 ns t lh low to high propagation delay, clk to clk to ptyerr 1.2 3 ns t hl high to low propagation delay, clk to clk to ptyerr 13ns t phl high to low propagation delay, reset to qn 3ns t plh low to high propagation delay, reset to ptyerr 3ns
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 11 idt74sstubf32865a 7092/10 output buffer characteristics output edge rates over recommended operating free-air temperature range parameter v dd = 1.8v 0.1v units min. max. dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt_ 1 1 difference between dv/dt_ r (rising edge rate ) and dv/dt_f (falling edge rate). 1v/ns
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 12 idt74sstubf32865a 7092/10 parity logic diagram register timing ptyerr parin dn d q d d d clock latching and reset function qna qnb 22 22 clk clk dn parin qn ptyerr t pdm, t pdmss n-1 n n+1 n+2 n+3 n+4 n+5 t su t h t su t h t pdm t pdh
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 13 idt74sstubf32865a 7092/10 test circuits and waveforms (v dd = 1.8v 0.1v) simulation load circuit voltage and current waveforms inputs active and inactive times voltage waveforms - pulse duration voltage waveforms - setup and hold times production-test load circuit voltage waveforms - propagation delay times voltage waveforms - propagation delay times notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v dd /2 6. v ih = v ref + 250mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600mv. 9. t plh and t phl are the same as t pdm . c l =12pf r l =1k dut out r l= 100 clk inputs t l =50 t l = 350ps, 50 test point clk clk v dd r l =1k test point test point v dd 0v v dd /2 lvcmos reset input i dd v dd /2 t inact t act 10% 90% v icr v id v icr input t w v ref v ih v il v ref input v icr v id t su t h clk clk z o =50 test point r l =50 dut out clk inputs clk v dd /2 clk z o =50 z o =50 test point test point clk v icr v id t plh t phl output v oh v ol v icr v tt v tt clk v oh v ol v ih v il t rphl v dd /2 v tt lvcmos reset input output
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 14 idt74sstubf32865a 7092/10 test circuits and waveforms (v dd = 1.8v 0.1v) load circuit: high-to-l ow slew-rate adjustment voltage waveforms: high-to-low slew-rate adjustment load circuit: low-to-h igh slew-rate adjustment voltage waveforms: low-to-h igh slew-rate adjustment load circuit: error output measurements voltage waveforms: open drain output low-to-high transition time (w ith respect to reset input) voltage waveforms: open drain output high-to-low transition time (with r espect to clock inputs) voltage waveforms: open drain output low-to-high transition time (with r espect to clock inputs) notes: 1. cl includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). c l =10pf r l =50 dut out test point v dd v oh 80% 20% v ol output dv_f dt_f c l =10pf r l =50 dut out test point v ol 20% 80% v oh output dv_r dt_r c l =10pf r l =1k dut out test point v dd v oh v cc output waveform 2 lvcmos reset input t plh v cc /2 0.15v 0v 0v v cc v icr t hl timing inputs v icr v i(pp) output waveform 1 v cc /2 v ol v oh output waveform 2 0.15v 0v v icr t hl timing inputs v icr v i(pp)
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 15 idt74sstubf32865a 7092/10 package outline and pack age dimensions - bga package dimensions are kept current with jedec publication no. 95 1 h t d d n p r t u g h j k l m b c d e f 2 3 4 5 6 7 8 9 10 11 12 row a, column 1 e 0.925 ref 0.975 ref e a v typ 0.10 c b c all dimensions in millimeters d 13.00 bsc e 9.00 bsc t min/max 1.10/1.30 e 0.65 bsc d min/max 0.35/0.45 h min/max 0.27/0.37 b 0.975 c 0.925 ref. dims ball grid note: ball grid total indicates maximum ball count for package. lesser quantity may be used. horiz 12 vert 18 total 160
idt74sstubf32865a 28-bit 1:2 registered buffer with p arity commercial temperature grade 28-bit 1:2 registered buffer with parity 16 idt74sstubf32865a 7092/10 ordering information xxx xx package device type bkg thin profile, fine pitch, ball grid array - green 28-bit 1:2 registered buffer with parity 865a 32 double density idt xx family shipping carrier x 8 tape and reel sstubf xx temp. range 74 0c to +70c (commercial)
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 innovate with idt and accelerate your future netw orks. contact: www.idt.com idt74sstubf32865a 28-bit 1:2 registered buffer with parity commercial temperature grade

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